Board parameters update

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Board parameters update

Werner Almesberger
Here's an update of the number of components we'll need and the structure
of the PCB:

- PCB size is about 10 x 6 cm2.
- PCB has 8 layers, 1 mm overall thickness. (*)
- Minimum trace width is 4 mil, with a 4 mil clearance between traces
  and between traces and pads.
- Surface finish is ENIG
- For the board structure, we need input from the PCB factory. Openmoko
  used a core of FR4 to which layers of PP 1080 65% and PP 1078 61% were
  added.
- PCB has components on both sides, about 10% on one, 90% on the other.
- Total number of components on the PCB will be about 400.
- Approximately 140 of the components on the PCB are unique.
- There are about 20 components that don't have a standard chip
  package (connectors, buttons, shields, etc.)
- Largest components are a 27 x 18 mm2 SIM/SD combi-cardholder, and a
  22 x 22 x 3 mm3 BGA module.
- Largest chip is a 14 x 14 mm2, 0.5 mm pitch 332-FBGA (SC32442)
- Smallest component is 0402.

(*) I'd like to try to make this work with only 6 layers, but I'm not
    sure if that's possible. Our circuit is considerably simpler than
    Openmoko's, with a greatly simplified memory bus and GSM in a
    module, so there is hope.

- Werner

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Re: Board parameters update

AlvieBoy
Werner Almesberger wrote:

> (*) I'd like to try to make this work with only 6 layers, but I'm not
>     sure if that's possible. Our circuit is considerably simpler than
>     Openmoko's, with a greatly simplified memory bus and GSM in a
>     module, so there is hope.

How are we to use those layers ? Which will be mostly ground, vcc, and routing ?

Shall we use OM approach ? I also think we can do it with a 6-layer, as long as we can use buried and blind vias.

Álvaro

>
> - Werner
>
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Re: Board parameters update

Laszlo KREKACS
On Thu, Aug 27, 2009 at 5:13 PM, Álvaro Lopes<[hidden email]> wrote:
> ... as long as we can use buried and blind vias.

Hmm, it does not make our life more difficult? (hard to debug if needed)

Best regards,
 Laszlo

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Re: Board parameters update

Werner Almesberger
In reply to this post by AlvieBoy
?lvaro Lopes wrote:
> How are we to use those layers ? Which will be mostly ground, vcc, and
> routing ?

I was thinking of something like this (assuming six layers):

- TOP (LCM side): components, local routing, and test pads
- L1: power (routing if necessary)
- L2: ground (less strict)
- L3: routing
- L4: ground (strict)
- BOTTOM (battery side): components and local routing

That way, we can "sandwich" EMI-sensitive traces between ground planes
in layer 3.

But ... I've never designed a multilayer board myself, let alone one
with RF subsystems, so my ideas may be totally wrong.

> Shall we use OM approach ?

Hmm, what would that be ?

> I also think we can do it with a 6-layer, as long as we can use
> buried and blind vias.

Blind vias should be no problem. I would try to avoid buried vias
if we can. Not only because they may make the board harder to
manufacture, but also because they effectively hide a trace from
measurements.

- Werner

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Re: Board parameters update

AlvieBoy
Werner Almesberger wrote:

> ?lvaro Lopes wrote:
>> How are we to use those layers ? Which will be mostly ground, vcc, and
>> routing ?
>
> I was thinking of something like this (assuming six layers):
>
> - TOP (LCM side): components, local routing, and test pads
> - L1: power (routing if necessary)
> - L2: ground (less strict)
> - L3: routing
> - L4: ground (strict)
> - BOTTOM (battery side): components and local routing
>
> That way, we can "sandwich" EMI-sensitive traces between ground planes
> in layer 3.

Not good for RF lines - vias introduce a lot of reflection. But might be good for other signals.

> But ... I've never designed a multilayer board myself, let alone one
> with RF subsystems, so my ideas may be totally wrong.
>
>> Shall we use OM approach ?
>
> Hmm, what would that be ?

From a quick inspection:

BOTTOM: components + routing
L7: ground (less strict)
L6: routing + ground
L5: ground (strict) ??
L4: (power routing ?)
L3: ground (strict) ??
L2: power
TOP: components, routing


>
>> I also think we can do it with a 6-layer, as long as we can use
>> buried and blind vias.
>
> Blind vias should be no problem. I would try to avoid buried vias
> if we can. Not only because they may make the board harder to
> manufacture, but also because they effectively hide a trace from
> measurements.

Current design has many. Not sure we can avoid buried vias at all.

Álvaro

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Re: Board parameters update

Werner Almesberger
?lvaro Lopes wrote:
> Not good for RF lines - vias introduce a lot of reflection.

So you'd keep RF on the surface ? And RF signals crossing a can
boundary get a hole in the can ? I now see that this seems to be
what has been done with GPS.

> BOTTOM: components + routing
> L7: ground (less strict)
> L6: routing + ground
> L5: ground (strict) ??
> L4: (power routing ?)
> L3: ground (strict) ??
> L2: power
> TOP: components, routing

So you'd start with 8 layers and then see if two of them end up
bring avoidable ?

> Current design has many. Not sure we can avoid buried vias at all.

The fewer layers we have, the less difference there is between a
buried and a blind via ;-))

- Werner

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Re: Board parameters update

AlvieBoy
Werner Almesberger wrote:
> ?lvaro Lopes wrote:
>> Not good for RF lines - vias introduce a lot of reflection.
>
> So you'd keep RF on the surface ? And RF signals crossing a can
> boundary get a hole in the can ? I now see that this seems to be
> what has been done with GPS.

Yes, that's exactly it. Same reason to avoid 90 degree direction changes in RF lines - reflection.

>> BOTTOM: components + routing
>> L7: ground (less strict)
>> L6: routing + ground
>> L5: ground (strict) ??
>> L4: (power routing ?)
>> L3: ground (strict) ??
>> L2: power
>> TOP: components, routing
>
> So you'd start with 8 layers and then see if two of them end up
> bring avoidable ?

No, I think we should start with a 6 layer. Unless someone disagrees. I was just stating what I think is current FR PCB layer structure.

>
>> Current design has many. Not sure we can avoid buried vias at all.
>
> The fewer layers we have, the less difference there is between a
> buried and a blind via ;-))

True, true :)

Álvaro

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Re: Board parameters update

Werner Almesberger
?lvaro Lopes wrote:
> Yes, that's exactly it. Same reason to avoid 90 degree direction
> changes in RF lines - reflection.

Aah, nice. Yet another thing learned :) Thanks !

> No, I think we should start with a 6 layer. Unless someone disagrees.
> I was just stating what I think is current FR PCB layer structure.

I never quite analyzed the Gerbers to a lot of detail, but what you
wrote sounds about right, except that both L6 and L7 seem to have a
lot of routing.

So, how do we get started. Shall I do another conversion from
http://downloads.openmoko.org/developer/schematics/GTA02/gta02_outline_footprints_netlist.tar.bz2
this time with the can outlines as well ?

Also, what should be the board orientation ? LCM side up like
Openmoko did or battery side up ? Almost all of the components are
at the "bottom", so the latter may be easier to work with.

Last but not least, board orientation. I think landscape is best,
given that screens are wider than tall. GPS to the right ?

- Werner

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Re: Board parameters update

AlvieBoy
Werner Almesberger wrote:
> I never quite analyzed the Gerbers to a lot of detail, but what you
> wrote sounds about right, except that both L6 and L7 seem to have a
> lot of routing.

Yes, routing + fill with ground afaics.

> So, how do we get started. Shall I do another conversion from
> http://downloads.openmoko.org/developer/schematics/GTA02/gta02_outline_footprints_netlist.tar.bz2
> this time with the can outlines as well ?

If we're using those same cans, yes, it will help a lot.

> Also, what should be the board orientation ? LCM side up like
> Openmoko did or battery side up ? Almost all of the components are
> at the "bottom", so the latter may be easier to work with.

Not sure, same for me.

> Last but not least, board orientation. I think landscape is best,
> given that screens are wider than tall. GPS to the right ?

Can be :)

Álvaro

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Re: Board parameters update

Rene Harder
In reply to this post by Werner Almesberger
According to our financial situation right now, it's might be worth to
tweak some board parameters to reduce production cost.

I think we should try to stay as much within common standard specs as
possible because the goal of gta02-core is to create a prototype and we
are not going for production right away. Custom specs always means that
our board has to be processed individually which adds up to higher cost.

So here are a few comments where i think we can cut costs.

Werner Almesberger wrote:
> Here's an update of the number of components we'll need and the structure
> of the PCB:
>
> - PCB size is about 10 x 6 cm2.
> - PCB has 8 layers, 1 mm overall thickness. (*)
> - Minimum trace width is 4 mil, with a 4 mil clearance between traces
>   and between traces and pads.
>  

Is 4 mil really necessary? Most fabs go down to 5-6mil as min.
Trace/Space width. I believe we can find a fab who can make boards with
4mil but that require a more precision fabrication process as well makes
it electrical and optical test absolutely necessary. Although most fabs
will require an electrical test for board with equal or more than 6 layers.

> - Surface finish is ENIG
>  

I think for a prototype a regular chemical or HAL tin finish might be
sufficient or are the any specific reasons why we need ENIG.

> - For the board structure, we need input from the PCB factory. Openmoko
>   used a core of FR4 to which layers of PP 1080 65% and PP 1078 61% were
>   added.
>  

I guess 1080 woven-glass with 65% FR4 epoxy laminate is pretty much
standard everywhere so shouldn't be too difficult to get. About 1078
prepreg im not sure, haven't seen it anywhere in the specs so this might
be only possible within custom specs.
> - PCB has components on both sides, about 10% on one, 90% on the other.
> - Total number of components on the PCB will be about 400.
> - Approximately 140 of the components on the PCB are unique.
>  
First of all I've not much experience with SMT assembly fabs, so if I'm
wrong please correct me.

Are we planning on population all components in a fab? 140 unique
components, that's quite much and I think this means an increase of
setup costs for the placements. So maybe it's worth to solder some
unique components our own, if that would reduce the costs.

Another thing, for the assembly fab we would need a square/rectangle
board so we should keep in mind that we need to panelize the board with
an additional outer frame.



> - There are about 20 components that don't have a standard chip
>   package (connectors, buttons, shields, etc.)
> - Largest components are a 27 x 18 mm2 SIM/SD combi-cardholder, and a
>   22 x 22 x 3 mm3 BGA module.
> - Largest chip is a 14 x 14 mm2, 0.5 mm pitch 332-FBGA (SC32442)
> - Smallest component is 0402.
>
> (*) I'd like to try to make this work with only 6 layers, but I'm not
>     sure if that's possible. Our circuit is considerably simpler than
>     Openmoko's, with a greatly simplified memory bus and GSM in a
>     module, so there is hope.
>  
6 layer would be good to cut costs, every additional layer increases
production cost.

For solder stop mask and silk screen i think they don't make much of a
difference in production cost usually you have to pay a small setup fee
for the whole batch if it's not included.


A serious problem are blind and buried vias though. They are our killer
for any standard specs, if I'm not mistaken they require a huge amount
of extra steps between every lamination process which is impossible to
do within standard spec. So best would be to stick to PTH vias if that's
not possible our cost will be probably more than doubled.

Just a an example a board with our size, 6 layer, 6 mil Trace/Space, all
holes platted through, quantity 15 pcs. is about $80 USD/ per board
(board outline routing is only rectangle though)

For a board with our current specs 8 layer, ENIG, burried and blind
vias, we would need to get a custom quote (which usually needs a final
board layout). But i do think Werner's estimation is not far away from
the real cost so we would end up around $250-300/per board.

At the end, i think we should consider that this will be *only* a
prototype and not a usable phone, so we don't need a lot of gimmicks
which are not absolutely required.

Rene


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Re: Board parameters update

Werner Almesberger
Rene Harder wrote:
> I think we should try to stay as much within common standard specs as
> possible because the goal of gta02-core is to create a prototype and we
> are not going for production right away. Custom specs always means that
> our board has to be processed individually which adds up to higher cost.

Agreed. The easier we can make the board to produce, the more choices
and the lower the price. My estimates are based on the assumption that
the simpler circuit will help us to make a slightly less demanding
board than Openmoko's original, but that there won't be any
revolutionary simplifications.

If we can "dumb" down the layout drastically, that's great. It's just
not something I'd feel comfortable assuming when making cost estimates
or when evaluating an SMT site.

> Is 4 mil really necessary? Most fabs go down to 5-6mil as min.
> Trace/Space width.

The track width is constrained mainly by the BGAs. If the 2442 is our
most demanding component, then 5 mil may be enough: the ball to ball
pitch is 0.5 mm, with a ball diameter of 0.3 mm, footprint equal to
pad size.

As far as I can tell, it's unavoidable to route diagonally between
balls (e.g., B2, B25, etc.), so we have to fit a trace into
0.5 mm * sqrt(2) - 0.3 mm = 0.4 mm or 15.7 mil.
5 mil would be enough for this.

> I think for a prototype a regular chemical or HAL tin finish might be
> sufficient or are the any specific reasons why we need ENIG.

I have to admit that I'm not an expert on surface finishes. I did a
bit of Web research a while ago and found the following:

- HAL/HASL: cheap and easily available but with a relatively uneven
  surface. A potential problem for fine-pitch BGA. (There, we need
  better than 99.9% accuracy, or each of the boards will end up with
  some random flaw or another.)

- OSP (Organic): inexpensive and with great surfaces, but unstable
  and demanding on process parameters. With OSP, I would mainly be
  worried about test pads oxydizing and becoming unsolderable. It
  probably also constrains the choice of SMT fabs. OSP seems to be a
  good choice when optimizing the board cost over large quantities.

- ENIG (Nickel-Gold): the standard process for anything demanding.
  Old and well understood. Boards can take some abuse, such as heat,
  storage, or oxygen. Needs two process steps and is more expensive
  than the rest.

- Immersion Silver: a relatively new coating that competes with ENIG.
  Less expensive but susceptible to oxydation. Suitable for
  fine-pitch packages.

So ENIG seems to be the safest choice, particularly if we assume that
we may have to do significant rework. HASL doesn't seem to be suitable
for small-pitch, or it's at least risky. OSP looks more like the thing
you consider for mass production. Silver may be a possibility. I'm not
sure how delicate the handling is, though, and how quickly oxydation
would become a problem with test pads and unpopulated footprints.

> I guess 1080 woven-glass with 65% FR4 epoxy laminate is pretty much
> standard everywhere so shouldn't be too difficult to get. About 1078
> prepreg im not sure, haven't seen it anywhere in the specs so this might
> be only possible within custom specs.

The board is quite thin, only 1 mm. That may complicate it somewhat.
Going to 6 layers should bring us closer to standard thicknesses.
Besides that, I think we can adapt the layout to a wide range of
parameters.

> Are we planning on population all components in a fab? 140 unique
> components, that's quite much and I think this means an increase of
> setup costs for the placements. So maybe it's worth to solder some
> unique components our own, if that would reduce the costs.

I would leave out the shields (they can easily cause trouble and get
in the way of rework). If any of the electromechanical components
cause trouble, manually soldering them may be an option.

One thing to consider is that we need to have everything we want to
test at the SMT site on the board. Otherwise, the boards cannot be
tested on-site.

> Another thing, for the assembly fab we would need a square/rectangle
> board so we should keep in mind that we need to panelize the board with
> an additional outer frame.

Yup. That has to be specified by the fab.

> A serious problem are blind and buried vias though. They are our killer
> for any standard specs, if I'm not mistaken they require a huge amount
> of extra steps between every lamination process which is impossible to
> do within standard spec. So best would be to stick to PTH vias if that's
> not possible our cost will be probably more than doubled.

Hmm, I'm not sure we'll be able to pull this off with through vias.
Also, don't they increase the EMI risk by spreading signals all over
the place ?

> At the end, i think we should consider that this will be *only* a
> prototype and not a usable phone, so we don't need a lot of gimmicks
> which are not absolutely required.

Yes, but on the other hand, we wouldn't want to use a very fragile
processa that introduces problems we could have avoided. There's this
moment when you try to power up a new board and nothing works. It
really helps then if you don't have to suspect every single solder
joint to be a traitor to the cause ;-)

- Werner

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Re: Board parameters update

AlvieBoy
In reply to this post by Rene Harder
Rene Harder wrote:
> So here are a few comments where i think we can cut costs.

> Is 4 mil really necessary? Most fabs go down to 5-6mil as min.
> Trace/Space width. I believe we can find a fab who can make boards with
> 4mil but that require a more precision fabrication process as well makes
> it electrical and optical test absolutely necessary. Although most fabs
> will require an electrical test for board with equal or more than 6 layers.

No, we can live with 5mil. Unless the RF traces require smaller tracks, but we can overcome that.

> I think for a prototype a regular chemical or HAL tin finish might be
> sufficient or are the any specific reasons why we need ENIG.

> I guess 1080 woven-glass with 65% FR4 epoxy laminate is pretty much
> standard everywhere so shouldn't be too difficult to get. About 1078
> prepreg im not sure, haven't seen it anywhere in the specs so this might
> be only possible within custom specs.

We should get quotes from some manufactures about the prepreg. Actually we need that to properly design RF.

> 140 unique components, that's quite much

I don't think so. There are machines that can handle more than that.

> For solder stop mask and silk screen i think they don't make much of a
> difference in production cost usually you have to pay a small setup fee
> for the whole batch if it's not included.

Define 'small' :)

> A serious problem are blind and buried vias though. They are our killer
> for any standard specs, if I'm not mistaken they require a huge amount
> of extra steps between every lamination process which is impossible to
> do within standard spec. So best would be to stick to PTH vias if that's
> not possible our cost will be probably more than doubled.

PTH vias present other problems too. We can probably like with PTH though, but I'd like at least to have microvias for the FBGA. But all this depends on how we
decide to use the layers.

> Just a an example a board with our size, 6 layer, 6 mil Trace/Space, all
> holes platted through, quantity 15 pcs. is about $80 USD/ per board
> (board outline routing is only rectangle though)


plated through, and filled with insulator or conductor?

> For a board with our current specs 8 layer, ENIG, burried and blind
> vias, we would need to get a custom quote (which usually needs a final
> board layout). But i do think Werner's estimation is not far away from
> the real cost so we would end up around $250-300/per board.
>
> At the end, i think we should consider that this will be *only* a
> prototype and not a usable phone, so we don't need a lot of gimmicks
> which are not absolutely required.

Yes, but we should get as close as the "final product" as possible.

Álvaro

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Re: Board parameters update

Rene Harder
In reply to this post by Werner Almesberger
Werner Almesberger wrote:

> Rene Harder wrote:
>  
>> I think for a prototype a regular chemical or HAL tin finish might be
>> sufficient or are the any specific reasons why we need ENIG.
>>    
>
> I have to admit that I'm not an expert on surface finishes. I did a
> bit of Web research a while ago and found the following:
>
> - HAL/HASL: cheap and easily available but with a relatively uneven
>   surface. A potential problem for fine-pitch BGA. (There, we need
>   better than 99.9% accuracy, or each of the boards will end up with
>   some random flaw or another.)
>
> - OSP (Organic): inexpensive and with great surfaces, but unstable
>   and demanding on process parameters. With OSP, I would mainly be
>   worried about test pads oxydizing and becoming unsolderable. It
>   probably also constrains the choice of SMT fabs. OSP seems to be a
>   good choice when optimizing the board cost over large quantities.
>
> - ENIG (Nickel-Gold): the standard process for anything demanding.
>   Old and well understood. Boards can take some abuse, such as heat,
>   storage, or oxygen. Needs two process steps and is more expensive
>   than the rest.
>
> - Immersion Silver: a relatively new coating that competes with ENIG.
>   Less expensive but susceptible to oxydation. Suitable for
>   fine-pitch packages.
>
> So ENIG seems to be the safest choice, particularly if we assume that
> we may have to do significant rework. HASL doesn't seem to be suitable
> for small-pitch, or it's at least risky. OSP looks more like the thing
> you consider for mass production. Silver may be a possibility. I'm not
> sure how delicate the handling is, though, and how quickly oxydation
> would become a problem with test pads and unpopulated footprints.
>  

Hmm not sure here,  I would use ENIG for production because it's a
reliable and stable process for many years now. So you probably will not
end up with a lot of faulty or useless boards.

The chemical deposition of organometallic compounds (OSP) is becoming
more and more popular, and you'll find it in prototype spec quite often
these days. However I have no idea about long time stability (have never
used it myself)

>  
>> I guess 1080 woven-glass with 65% FR4 epoxy laminate is pretty much
>> standard everywhere so shouldn't be too difficult to get. About 1078
>> prepreg im not sure, haven't seen it anywhere in the specs so this might
>> be only possible within custom specs.
>>    
>
> The board is quite thin, only 1 mm. That may complicate it somewhat.
> Going to 6 layers should bring us closer to standard thicknesses.
> Besides that, I think we can adapt the layout to a wide range of
> parameters.
>  

Indeed, that makes things more complicated However, there are companies
who have boards with an overall thickness of 0.31" or 0.40" for 6
layer[1] or 0.48" for 8 layer[2] in their standard specs. Sure you can
build you own board with an individual stack-up [3], but that means a
custom design again.

>
>> A serious problem are blind and buried vias though. They are our killer
>> for any standard specs, if I'm not mistaken they require a huge amount
>> of extra steps between every lamination process which is impossible to
>> do within standard spec. So best would be to stick to PTH vias if that's
>> not possible our cost will be probably more than doubled.
>>    
>
> Hmm, I'm not sure we'll be able to pull this off with through vias.
> Also, don't they increase the EMI risk by spreading signals all over
> the place ?
>
>  

Actually neither do I and It probably will get really messy around the
BGAs ;-)
Well, yeah they'll make a swiss cheese out of our image planes, which
results in an increase of their impedance.

>> At the end, i think we should consider that this will be *only* a
>> prototype and not a usable phone, so we don't need a lot of gimmicks
>> which are not absolutely required.
>>    
>
> Yes, but on the other hand, we wouldn't want to use a very fragile
> processa that introduces problems we could have avoided. There's this
> moment when you try to power up a new board and nothing works. It
> really helps then if you don't have to suspect every single solder
> joint to be a traitor to the cause ;-)

Sure, i don't suggest that we have to use a fragile or instable process.
I just think that it's worth to check what features are really necessary
and what's their benefit over different/similar technologies.
 

[1] http://www.4pcb.com/media/031-%206%20Layer.pdf
[2] http://www.4pcb.com/media/048%208%20layer%20copy.pdf
[3] http://www.4pcb.com/media/PrePreg%20Thickness%20chart.pdf

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Re: Board parameters update

AlvieBoy
Rene Harder wrote:

>> Hmm, I'm not sure we'll be able to pull this off with through vias.
>> Also, don't they increase the EMI risk by spreading signals all over
>> the place ?
>>
>>  
>
> Actually neither do I and It probably will get really messy around the
> BGAs ;-)
> Well, yeah they'll make a swiss cheese out of our image planes, which
> results in an increase of their impedance.

I just took a look at some echocanceller board with FBGA. All vias are PTH. Many lay unconnected on bottom side of FBGA.

Álvaro

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Re: Board parameters update

Rene Harder
In reply to this post by AlvieBoy
Álvaro Lopes wrote:

> Rene Harder wrote:
>  
>> So here are a few comments where i think we can cut costs.
>>    
>
>  
>> Is 4 mil really necessary? Most fabs go down to 5-6mil as min.
>> Trace/Space width. I believe we can find a fab who can make boards with
>> 4mil but that require a more precision fabrication process as well makes
>> it electrical and optical test absolutely necessary. Although most fabs
>> will require an electrical test for board with equal or more than 6 layers.
>>    
>
> No, we can live with 5mil. Unless the RF traces require smaller tracks, but we can overcome that.
>  

If I'm not completely off we should end up with a trace width around
8-15mil (50Ohms).

>  
>> I think for a prototype a regular chemical or HAL tin finish might be
>> sufficient or are the any specific reasons why we need ENIG.
>>    
>
>  
>> I guess 1080 woven-glass with 65% FR4 epoxy laminate is pretty much
>> standard everywhere so shouldn't be too difficult to get. About 1078
>> prepreg im not sure, haven't seen it anywhere in the specs so this might
>> be only possible within custom specs.
>>    
>
> We should get quotes from some manufactures about the prepreg. Actually we need that to properly design RF.
>
>  
>> 140 unique components, that's quite much
>>    
>
> I don't think so. There are machines that can handle more than that.
>  

It's not about the handling, It's more related to the cost. Someone has
to setup the assembly machine (change reels, setup placements etc.) and
if you have a lot of different components you will increase these setup
costs. However for a full production series that should not be a big
issue because this will be a one time fee averaged over all boards but
for a small prototype series this will probably be the main part of the
costs.

>  
>> For solder stop mask and silk screen i think they don't make much of a
>> difference in production cost usually you have to pay a small setup fee
>> for the whole batch if it's not included.
>>    
>
> Define 'small' :)
>  

less than 1% of the total board costs.

>  
>> A serious problem are blind and buried vias though. They are our killer
>> for any standard specs, if I'm not mistaken they require a huge amount
>> of extra steps between every lamination process which is impossible to
>> do within standard spec. So best would be to stick to PTH vias if that's
>> not possible our cost will be probably more than doubled.
>>    
>
> PTH vias present other problems too. We can probably like with PTH though, but I'd like at least to have microvias for the FBGA. But all this depends on how we
> decide to use the layers.
>  

Microvias are even worse then buried or blind vias those requires
special equipment for the fab (laser drills) and a quite complicated
process.
So i would rather use blind or buried vias! Although microvias will make
our live easier then we can embed them into the BGA pads.

>  
>> Just a an example a board with our size, 6 layer, 6 mil Trace/Space, all
>> holes platted through, quantity 15 pcs. is about $80 USD/ per board
>> (board outline routing is only rectangle though)
>>    
>
>
> plated through, and filled with insulator or conductor?
>  

all holes are platted through and not tented or filled with anything.

>  
>> For a board with our current specs 8 layer, ENIG, burried and blind
>> vias, we would need to get a custom quote (which usually needs a final
>> board layout). But i do think Werner's estimation is not far away from
>> the real cost so we would end up around $250-300/per board.
>>
>> At the end, i think we should consider that this will be *only* a
>> prototype and not a usable phone, so we don't need a lot of gimmicks
>> which are not absolutely required.
>>    
>
> Yes, but we should get as close as the "final product" as possible.
>  

I agree, but a prototype is only one step to the final product and
supposed to minimize the risk and costs of failures.
I doubt that anyone can design a product without prototyping and
honestly, I believe that this one will not be the last one for gta02-core.

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Re: Board parameters update

AlvieBoy
Rene Harder wrote:
> If I'm not completely off we should end up with a trace width around
> 8-15mil (50Ohms).

I think so, but will depend on insulator layers and how we chose the ground layers too. But yes.

> It's not about the handling, It's more related to the cost. Someone has
> to setup the assembly machine (change reels, setup placements etc.) and
> if you have a lot of different components you will increase these setup
> costs. However for a full production series that should not be a big
> issue because this will be a one time fee averaged over all boards but
> for a small prototype series this will probably be the main part of the
> costs.

Understood.

> Microvias are even worse then buried or blind vias those requires
> special equipment for the fab (laser drills) and a quite complicated
> process.
> So i would rather use blind or buried vias! Although microvias will make
> our live easier then we can embed them into the BGA pads.

That was the idea, yes, but we can live without that for the first prototypes.

> all holes are platted through and not tented or filled with anything.

I read something about filling them here [1]. Hence the question.

> I doubt that anyone can design a product without prototyping and
> honestly, I believe that this one will not be the last one for gta02-core.

It's just a prototype for now, we want to rule the world, so surely we'll improve the design quite a few times :)

Best,
Álvaro

[1] http://www.abraci.org.br/arquivos/ViainPadandPlanarizationTechnologyof24-07-2008.pdf

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Re: Board parameters update

Werner Almesberger
In reply to this post by Rene Harder
Rene Harder wrote:
> The chemical deposition of organometallic compounds (OSP) is becoming
> more and more popular, and you'll find it in prototype spec quite often
> these days. However I have no idea about long time stability (have never
> used it myself)

All I know about OSP I learned on the Web ;-) How do unsoldered pads
perform (NC, test pads) ? Can you leave them "clean" or do you apply
solder paste as a protection ?

Also, with stability, I'm less concerned about whether the board will
still work in ten years, but how long we can store it between PCB and
SMT. If that time is very short, that may be a problem. There are
always surprises ...

> Indeed, that makes things more complicated However, there are companies
> who have boards with an overall thickness of 0.31" or 0.40" for 6
> layer[1] or 0.48" for 8 layer[2] in their standard specs.

This board is begging for six layers ;-)

- Werner

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Re: Board parameters update

Rene Harder
Werner Almesberger wrote:

> Rene Harder wrote:
>  
>> The chemical deposition of organometallic compounds (OSP) is becoming
>> more and more popular, and you'll find it in prototype spec quite often
>> these days. However I have no idea about long time stability (have never
>> used it myself)
>>    
>
> All I know about OSP I learned on the Web ;-) How do unsoldered pads
> perform (NC, test pads) ? Can you leave them "clean" or do you apply
> solder paste as a protection ?
>
> Also, with stability, I'm less concerned about whether the board will
> still work in ten years, but how long we can store it between PCB and
> SMT. If that time is very short, that may be a problem. There are
> always surprises ...
>
>  

I agree, these are interesting questions, unfortunately I cannot give
you an proper answer. My Electronic Materials and Processes Handbook
doesn't really handle OSP. There is a small section about organic
compound (e.g. conductive epoxies) as solder finish though, but this
seems to be an outdated technology (although the book is not too old,
it's from 2004). I guess it'll be time for a new one.

>> Indeed, that makes things more complicated However, there are companies
>> who have boards with an overall thickness of 0.31" or 0.40" for 6
>> layer[1] or 0.48" for 8 layer[2] in their standard specs.
>>    
>
> This board is begging for six layers ;-)
>  

Yes it really does. :-D


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