the pins M1 -> nCE and U1 -> nWP are not findable in the samsung data
sheets (in table 1-1 they appear as M1 -> /CE and U1 -> /WP). Also port
Y21 is in the schematics at NCON0 but in the data sheets it's always Y21
-> NCON. The rest of the CPU is ok.
> the pins M1 -> nCE and U1 -> nWP are not findable in the samsung data
> sheets (in table 1-1 they appear as M1 -> /CE and U1 -> /WP).
Okay, I found it. Just a bit of background (we had discussed this on
IRC): the issue here is that the MSP appendix shows nWP ("/WP")
connected to M1 and nCE ("/CE") connected J1, while the rest of the
data sheet has them on the balls mentioned above.
The solution is simple: the MSP ball assignment and in fact the
entire BGA footprint in the appendix (i.e., the stacked memory) is
different from that of the whole package. Funny, I always thought
the appendix just showed the balls that the memory signals were
actually routed to.
I'm not sure why Samsung are even showing us that footprint that's
only buried somewhere deep inside the package, but in any case, the
ball assignments there are only vaguely related to what comes out
at the PCB.
So, there's no problem here. Table 1-1, the Openmoko schematics, and
our S3C2442 symbol all agree.