Review of SDRAM K4M51323PE

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Review of SDRAM K4M51323PE

Hi all,

jut reviewed K4M51323PE and did some small fixed on DQM pins (they are inputs, but marked as bidir [1]).

I was not able to find the concrete datasheet but used K4M51323PC instead. According to naming convention, 'E' and 'C' depict generation, so this should not
affect (I think) behaviour of device.


[1] - This sentence in datasheet "DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency
is 0), but in read operation, it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)" might been misunderstood - It can be used for reads,
but it is still an input.

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